The invention relates generally to plasma etching. In particular, the invention relates to a method of etching oxide layers in semiconductor integrated circuits with a magnetically enhanced plasma etch reactor.
Modem silicon integrated circuits contain millions to tens of millions of interconnected semiconductor devices. Such a high level of integration has been achieved, at least in part, by decreasing the minimum feature sizes and by providing multiple wiring layers of horizontally extending metallization lines. Dielectric layers separate the wiring layers, which are selectively connected with small-area vertical metallization interconnects. In the case of a dielectric layer separating two metallization layers, the vertical interconnect is called a via when it makes the connection between these metallization layers. However, the vertical interconnect is called a contact hole when it connects the first metallization layer to the semiconductor devices built on the silicon substrate. This invention will be primarily described with respect to the formation of the via or contact holes by dry plasma etching. After such holes are etched, they are filled with a metallization, such as tungsten, thereby forming the vertical connection.
As will be explained below, etching of the via or contact holes is presenting increasing difficulty in advanced structures because of their decreasing widths and increasing aspect ratios. Since this invention is applicable to both via and contact etches (and other dielectric etch applications), the terms xe2x80x9cviaxe2x80x9d and xe2x80x9ccontactxe2x80x9d may be used nearly interchangeably in the following text hereafter without distinguishing specialized portions of the process specific to one or the other.
The inter-level dielectric has conventionally been composed of a silica-based oxide, whether it is silicon dioxide grown in a plasma CVD process using TEOS, or a borophosphate silicate glass (BPSG) deposited as a spin on glass, or other dielectric materials. More recently, low-k dielectric materials have been developed for use as inter-level dielectrics. Their lower dielectric constants offer the possibility of reduced capacitive coupling between horizontally or vertically adjacent lines, thus reducing cross talk, power consumption, and signal rise time. Low-k dielectrics have been proposed having varying compositions, some silicon-based, and other carbon-based.
A typical advanced via hole is illustrated in the cross-sectional view of FIG. 1. A lower dielectric layer 10 includes a metal feature 12, such as a metallization line for the underlying layer 10. An upper dielectric layer 14 is deposited on the lower dielectric layer 10 and the metal feature 12. A step of chemical mechanical polishing (CMP) may be used to planarize the top surface of the dielectric layer 14. A photoresist layer 16 is spun onto the upper dielectric layer 14 and dried, and photographic means are used to expose and develop a photomask aperture in the area overlying the metal feature 12 in which the via is to be formed. The original upper profile of the patterned photoresist prior to etching is shown by line 16xe2x80x2. A plasma etching step uses the patterned photoresist layer as a photomask to etch through the dielectric layer 14 to the underlying metal feature 12 to form a via hole 20. The step of etching the dielectric is usually referred to as oxide etching.
After the formation of the via hole 20, the photoresist is stripped, and metal is deposited into the via hole 20. The structure may be more complicated than that illustrated depending upon the special needs of different device manufacturers. The metal feature 12 may be a line rising above the dielectric layer 14 or may be a dual-damascene structure combining in the dielectric a horizontal trench and a connected vertical via. An etch stop layer may be formed between the lower and upper dielectric layer 10, 14 to allow the etching step to stop on the etch stop layer without sputtering the underlying metal. For fluorine-based plasma etching of silica, silicon nitride is a good etch stop layer. An anti-reflection coating may be formed between the upper dielectric layer 14 and the photoresist layer 16 to aid the resolution of the photographic step used in the patterning the photomask. These additional structural features are well known in the art. Their etching is typically performed in steps separate from the dielectric etching, and an integrated etching process needs to be developed to combine the different etching steps. The invention is primarily concerned with the dielectric etching, which presents the most formidable challenges.
The thickness of the dielectric layer 14 is generally in the range of 0.7 to 1.4 xcexcm. This thickness is not expected to decrease in advanced devices. The larger thicknesses including multiple depths of via holes are usually associated with more complex metallization structures, which offer increased device density with fewer processing steps. Via widths for chips under commercial development now may be as small as 0.18 xcexcm. Technology for 0.13 xcexcm widths is being developed. Widths of 0.10 xcexcm are expected in the not too distant future.
These increasingly small widths present etching problems, particularly in view of the dielectric thickness remaining essentially constant. The via holes 20 have increasingly high aspect ratios. The aspect ratio of a via hole is the ratio between the depth of the hole to the narrowest dimension of the hole in its upper portion. At the present time, aspect ratios of 4 or 5 are found in advanced chips. In future chips, the aspect ratio will increase to 8 or 10. Such high aspect ratios present a significant challenge to oxide etching because they require a highly anisotropic etch that reaches deeply into the hole. Etching of high aspect-ratio holes also requires higher etch selectivity to photoresist due to the reduction in the oxide etch rate at greater depths in the holes. The selectivity and anisotropy required in the oxide etch has been typically accomplished using a fluorocarbon plasma chemistry which deposits a protective polymer over non-oxide materials and all vertical sidewalls. On the other hand, the combination of the fluorine plasma and underlying oxygen in the presence of energetic ion bombardment breaks down the polymer that formed at the bottom of the silica hole being etched and exposes the underlying silica to the etchant that turns it into volatile components which are pumped out from the hole, thereby etching the hole. However, if too much polymer is formed, the hole nonetheless becomes plugged with polymer and etching stops before the bottom of the hole is reached. No amount of further etching under the same conditions is effective at completing the etching process. This deleterious result is called etch stop.
The photolithography needed for such narrow features typically relies upon deep ultra-violet (DUV) light. Photoresists are available which are sensitive to DUV radiation. The thickness of the photoresist must be limited to little more than the minimum hole width. Otherwise, the photolithography becomes defocussed over the depth of the photoresist. However, photoresist is usually a carbon-based polymer that is prone to some degree of etching by most etch chemistries. As a result, the depth of the photoresist decreases from the original profile 16xe2x80x2 shown in FIG. 1 to profile 16. Furthermore, in most etching chemistries, exposed corners are etched more quickly than planar surfaces so that the most severe selectivity problem is often manifested in facets 22 forming at the upper corners of the photoresist layer 16 around the patterned hole in the photomask. Etching of polymeric materials such as photoresist tends to produce facets that are much more curved than illustrated. A photoresist etching margin is given by the remaining height 24 on the sidewall of the photoresist 16 next to the patterned via hole 20. If the facets 22 reach the underlying upper dielectric layer 14, that is, the photoresist etching margin reaches zero, the critical dimension (CD) associated with the photomask is lost, and the upper portions of the via hole 20 become flared.
A further problem with low photoresist selectivity, particularly around the facets 22, is that high-energy particles sputter the photoresist, and the sputtered photoresist material is likely to redeposit on the upper sidewalls of the via. Such non-uniformly redeposited photoresist makes it difficult to control of the hole profile. For these reasons, the selectivity of the oxide etch relative to the photoresist must be kept high, and the most critical photoresist selectivity is that associated with the facets.
Photoresist selectivity has always been a concern in oxide etching, but nitride selectivity has usually been a greater concern. However, it appears that for very narrow structures, the photoresist selectivity will be the most difficult requirement imposed on the oxide etch.
Recent developments have shown that a fluorocarbon plasma can etch holes in oxide with aspect ratios up to about 5:1 with very high selectivity to nitride. Hung et al. have disclosed a particularly advantageous etching recipe in U.S. patent application, Ser. No. 09/276,311, filed Mar. 25, 1999, now U.S. Pat. No. 6,387,287 incorporated herein by reference in its entirety. This patent application discloses the advantage of using a heavy hydrogen-free fluorocarbon with a low F/C ratio, such as hexafluorobutadiene (C4 F6), as the active etchant species, in combination with a larger fraction of a carrier gas. Argon is the conventional carrier gas for plasma etching, but Hung et al. in U.S. patent applications, Ser. Nos. 09/276,376, filed Mar. 25, 1999 now allowed, and 09/405,869, filed Sep. 24, 1999 now allowed, have disclosed that even better nitride selectivity without etch stop is obtained if xenon is used as the carrier gas in combination with fluorocarbons such as C4F6. These patents are also incorporated herein by reference in their entireties.
The chemistry presented in the patents has been primarily developed on the IPS Etch Reactor, available from Applied Materials, Inc. of Santa Clara, Calif. The IPS reactor is a high-density plasma reactor using an inductively coupled plasma source to generate a high-density plasma (HDP), which is defined as one having an ionization density of at least 1011cmxe2x88x923 over the entire region of the plasma excluding the plasma sheath. In the IPS reactor, the RF inductive coil is primarily responsible for generating the plasma while another RF power supply applied to the pedestal electrode controls the DC self-bias voltage, thereby controlling the energy of the ions accelerated across the plasma sheath to the wafer. However, a desire still exists for performing oxide etching in more conventional capacitively coupled plasma etch reactors, often referred to as diode reactors. HDP reactors have only recently been developed and are still relatively expensive. Further, the high-density plasmas have the ability to create damage in semiconductor chips, for example, by charging the dielectric. While these damage mechanisms can usually be controlled in HDP reactors, they are much less of a problem in capacitively coupled reactors producing a lower plasma density.
An example of capacitively coupled etch reactor is the magnetically enhanced reactive ion etch (MERIE) reactor 30 schematically illustrated in FIG. 2. This illustration is based on the MxP, eMax, or Super-e etch reactors available from Applied Materials. It includes a grounded vacuum chamber 32, perhaps including liners to protect the walls. A wafer 34 is inserted into the chamber 32 through a slit valve opening 36 and placed on a cathode pedestal 38 with an electrostatic chuck 40 selectively clamping the wafer. The chuck powering is not illustrated. Unillustrated fluid cooling channels through the pedestal 38 maintain the pedestal at reduced temperatures. A thermal transfer gas such as helium is supplied to unillustrated grooves in the upper surface of the pedestal 38. The thermal transfer gas increases the efficiency of thermal coupling between the pedestal 38 and the wafer 34, which is held against the pedestal 38 by the electrostatic chuck 40 or an alternatively used peripheral wafer clamp.
An RF power supply 42, preferably operating at 13.56 MHz, is connected to the cathode pedestal 38 and provides the only significant power for generating the plasma while also controlling the DC self-bias. Magnetic coils 44 powered by unillustrated current supplies surround the chamber 32 and generate a slowly rotating (on the order of seconds and typically less than 10 ms), horizontal, essentially DC magnetic field in order to increase the density of the plasma. A vacuum pump system 46 pumps the chamber 32 through an adjustable throttle valve 48. Shields 50, 52 not only protect the chamber 32 and pedestal 38 but also define a baffle 54 and a pumping channel 54 connected to the throttle valve 48.
Processing gases are supplied from gas sources 58, 60, 62 through respective mass flow controllers 64, 66, 68 to a quartz gas distribution plate 70 positioned in the roof of the chamber 32 overlying the wafer 34 and separated from it across a processing region 72. The composition of the etching gas is a subject matter of one aspect of the present invention. The distribution plate 70 includes a manifold 74 receiving the processing gas and communicating with the processing region 72 through a showerhead having a large number of distributed apertures 76 so as to inject a more uniform flow of processing gas into the processing region 72.
The ""311 patent application discloses some preliminary results using C4F6 for etching oxide in a magnetically enhanced reactive ion etcher (MERIE), such as the MxP, eMax, or Super-e reactors. The favored recipe includes only C4F6 and large amounts of argon, but further work is deemed to be necessary to obtain a production worthy recipe and yet better performance.
The invention includes a process for etching dielectric oxides in a capacitively coupled plasma etch reactor using a heavy fluorocarbon such as hexafluorobutadiene (C4F6), oxygen, and a substantial fraction of a carrier gas, preferably argon. Carbon dioxide (CO) may additionally be added. The process is capable of providing high selectivity for etching oxide relative to photoresist and is thus particularly useful for etching very high aspect-ratio holes. The fluorocarbon is preferably hydrogen-free and has a low F/C ratio of less than 2, more preferably no more than 1.6 and most preferably no more than 1.5.
The invention also includes decreasing the magnetic field as the etched hole is deepening. It further includes decreasing the amount of oxygen relative to the fluorocarbon. The capability of this process to control the composition and conformal deposition of the polymer not only improves the profile control for high aspect ratio holes, but also the selectivities to the underlayers that made of materials other than SiO2, such as Si3N4, polysilicon, and metal silicide. This wide range of the plasma composition produced hereby is therefore suitable to all critical dielectric, such as SAC and dual damascene.